DocumentCode
2432193
Title
Research on design method of scalable Configurable IP Core
Author
Li, Lei ; Wang, Jian ; Wang, Yuan ; Lai, Jinmei
Author_Institution
ASIC & Syst. State Key Lab., Fudan Univ., Shanghai, China
fYear
2011
fDate
6-9 June 2011
Firstpage
50
Lastpage
57
Abstract
Aiming at improving the flexibility and reducing the cost of SOC system design, the design of configurable IP core is prerequisite. In this paper, we mainly design a scalable configurable IP core and its configurable interface circuit. We call it FDP (FuDan Programmable) Configurable IP Core. This IP Core meets the requirement of configuration and scalability. Based on FDP Configurable IP Core, we successfully embed it into SOC to realize the application of Evolvable Hardware. Meanwhile, in order to reduce the reconfiguration time and enhance the performance of the whole system, we adopt several methods such as pre-reading configuration and compression of configuration bit stream, to implement the hardware reconfiguration and realize the function effectively. Experimental results initially validate the feasibility and large potential of the embedded scalable Configurable IP Core.
Keywords
integrated circuit design; reconfigurable architectures; system-on-chip; FuDan programmable; SOC system design; configurable interface circuit; configuration bit stream; evolvable hardware; hardware reconfiguration; pre-reading compression; pre-reading configuration; scalable configurable IP core; Hardware; IP networks; Integrated circuit interconnections; Random access memory; Registers; Routing; System-on-a-chip;
fLanguage
English
Publisher
ieee
Conference_Titel
Adaptive Hardware and Systems (AHS), 2011 NASA/ESA Conference on
Conference_Location
San Diego, CA
Print_ISBN
978-1-4577-0598-4
Electronic_ISBN
978-1-4577-0597-7
Type
conf
DOI
10.1109/AHS.2011.5963966
Filename
5963966
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