DocumentCode
2432331
Title
An efficient multi-phase test technique to perfectly prevent over-detection of acceptable faults for optimal yield improvement via error-tolerance
Author
Hsieh, Tong-Yu ; Lee, Kuen-Jong ; Breuer, Melvin A.
Author_Institution
Dept. of Electr. Eng., Nat. Cheng Kung Univ., Tainan, Taiwan
fYear
2009
fDate
28-30 April 2009
Firstpage
255
Lastpage
258
Abstract
In many multimedia applications, some faults induce errors that are user-imperceptible and thus are acceptable. By not testing for these faults, the effective yield can be significantly increased based on the principle of error-tolerance. However, studies have shown that test patterns generated by a conventional ATPG procedure targeting only unacceptable faults also detect many acceptable faults, resulting in a significant degradation in achievable yield improvement. In this paper we present a multi-phase test technique that can perfectly prevent this over-detection problem. Solid theoretical derivations are provided to validate the effectiveness of this technique. Compared with previous work, only a much smaller number of test patterns are required and thus the required test cost can be much lower. Experimental results on benchmark circuits illustrate the high efficiency of this novel technique.
Keywords
automatic test pattern generation; fault simulation; integrated circuit testing; integrated circuit yield; ATPG; acceptable fault detection; error tolerance; multiphase test technique; optimal yield improvement; over detection prevention; Automatic test pattern generation; Benchmark testing; Circuit faults; Circuit testing; Degradation; Electrical fault detection; Error analysis; Fault detection; System-on-a-chip; Test pattern generators;
fLanguage
English
Publisher
ieee
Conference_Titel
VLSI Design, Automation and Test, 2009. VLSI-DAT '09. International Symposium on
Conference_Location
Hsinchu
Print_ISBN
978-1-4244-2781-9
Electronic_ISBN
978-1-4244-2782-6
Type
conf
DOI
10.1109/VDAT.2009.5158143
Filename
5158143
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