Performance optimization of dynamic CMOS circuits through transistor sizing

Author

Yelamarthi, Kumar

Author_Institution

Sch. of Eng. & Technol., Central Michigan Univ., Mount Pleasant, MI, USA

fYear

2014

fDate

6-7 Jan. 2014

Firstpage

1

Lastpage

5

Abstract

One of the predominately used circuit styles in high-performance VLSI systems is dynamic CMOS due to its advantage in speed. However, the rising magnitude of circuits implemented on a chip, along with shrinking device size and process variations have increased the complexity of implementing dynamic CMOS circuit efficiently. Answering this challenge, this paper proposes a performance optimization technique for dynamic CMOS circuits that operates based on a Schmitt Trigger and pseudo pMOS feedback keeper. When implemented using IBM 90nm CMOS process, the proposed optimization technique has shown an improvement in worst-case delay by 44.84%, delay uncertainty by 55%, delay sensitivity by 34%, and power consumption by 36% when compared to their initial performances.

Keywords

CMOS integrated circuits; MOSFET; VLSI; circuit complexity; circuit optimisation; IBM CMOS process; Schmitt trigger; circuit complexity; delay sensitivity; delay uncertainty; device size; dynamic CMOS circuit; high-performance VLSI systems; performance optimization technique; power consumption; process variations; pseudopMOS feedback keeper; size 90 nm; transistor sizing; worst-case delay; Benchmark testing; CMOS integrated circuits; CMOS technology; Delays; Optimization; Transistors; low-power; process variations; timing optimization; transistor sizing;

fLanguage

English

Publisher

ieee

Conference_Titel

Electronics, Computing and Communication Technologies (IEEE CONECCT), 2014 IEEE International Conference on

Conference_Location

Bangalore

Print_ISBN

978-1-4799-2318-2

Type

conf

DOI

10.1109/CONECCT.2014.6740358

Filename

6740358