Speed-efficient wide adders for VIRTEX FPGAs

Recently, reconfigurable hardware based on field programmable gate arrays (FPGAs) has been presented as a promising alternative for implementing cryptographic systems. One of the main limitations of this approach, with respect to ASIC realizations, is the relatively low reachable throughput because of arithmetic operators, such as adders and multipliers, with large operands. In this paper, an efficient addition scheme designed for VIRTEX FPGAs is presented that outperforms the commonly used Macro-generated ripple-carry scheme for the case in which long words have to be added. The proposed method uses appropriately placed by-pass elements to eliminate consistent routing delays from critical paths. A 128 bit adder realized as described here shows a gain in speed of up to 47% with respect to a conventional adder with an increase of just 28% in area occupancy.