DocumentCode
2434238
Title
Two phase clocked adiabatic static CMOS logic
Author
Anuar, Nazrul ; Takahashi, Yasuhiro ; Sekine, Toshikazu
Author_Institution
Grad. Sch. of Eng., Gifu Univ., Gifu, Japan
fYear
2009
fDate
5-7 Oct. 2009
Abstract
This paper demonstrates the low-energy operation of a two-phase clocked adiabatic static CMOS logic (2PASCL) on the basis of the results obtained in the simulation of a 4-bit ripple-carry adder (RCA) and D-flipflop employing 2PASCL circuit technology. Two-phase unsymmetrical power supply clocks are introduced to increase the logic transition level. Energy dissipation in the unsymmetrical clocked 2PASCL RCA and D-flipflop are 77.2% and 55.5% less than that in a static CMOS at transition frequencies of 10-100 MHz respectively.
Keywords
CMOS integrated circuits; adders; flip-flops; logic circuits; D-flipflop; energy dissipation; frequency 10 MHz to 100 MHz; logic transition level; ripple-carry adder circuit; storage capacity 4 bit; two-phase clocked adiabatic static CMOS logic; two-phase unsymmetrical power supply clocks; unsymmetrical clocked 2PASCL RCA; CMOS logic circuits; CMOS technology; Clocks; Diodes; Energy consumption; Energy dissipation; Logic circuits; Logic devices; Power supplies; Voltage;
fLanguage
English
Publisher
ieee
Conference_Titel
System-on-Chip, 2009. SOC 2009. International Symposium on
Conference_Location
Tampere
Print_ISBN
978-1-4244-4465-6
Electronic_ISBN
978-1-4244-4467-0
Type
conf
DOI
10.1109/SOCC.2009.5335671
Filename
5335671
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