Design and prototype of an image capturing and processing system for ERPSat-1 Pico Satellite

Small satellites have captured the imagination worldwide of satellite designer due to its exciting technological and economic possibilities. Thus, pico satellites team of research group on intelligent machines laboratory, is developing ERPSat-1, ENIS REGIM pico satellite 1, the first pico satellite of the engineering school of Sfax, Tunisia. ERPSat-1 has three basic missions such as ground station communication, inter-satellite communication and remote sensing. In this paper, we present the architecture of ERPSat-1 such as the command and data handling subsystem, the communication subsystem, electrical power subsystem and remote sensing subsystem. We describe in particular the use of an FPGA for pictures processing, captured by a CMOS camera, in order to be transmitted to the ground station or other pico satellites similar to ERPSat-1. The FPGA technology enables reconfiguration and evolution of hardware designs on board satellite.