Patterned Heterogeneous CMPs: The Case for Regularity-Driven System-Level Synthesis

The imminent limitations imposed by the utilizationwall phenomenon compel architects to introduce heterogeneity in on-chip systems. The existing approaches to system-level synthesis of chip multiprocessors (CMPs) typically ignore physical aspects, leading to degradation in efficiency during later design stages. In this work, we propose and study the concept of patterned heterogeneous CMPs to handle the complexity of synthesis and extenuate the severity of physical aspects in post-synthesis engineering. A patterned CMP is a variation of a tiled architecture, in which layout regularity is enforced by fixing the tile size. Nevertheless, individual tiles may be implemented with different patterns, enabling a parameterizable degree of heterogeneity, which we leverage for synthesis efficiency. The results of synthesis demonstrate the effectiveness of patterned heterogeneity, suggesting it as a powerful tool for mastering the complexity of future on-chip systems.