Diagnosis of Gate Delay Faults in the Presence of Clock Delay Faults

This paper presents a diagnosis method for gate delay faults in the presence of clock delay faults. The method deduces candidate faults using a single gate delay fault dictionary and a single clock delay fault dictionary, which contain the information of latest transition time of signals as well as output logic values. To reduce the diagnostic ambiguity we remove those faults from the candidate fault list which provide a contradiction between the circuit responses and responses stored in the dictionary. Since the dictionary is not generated by considering the simultaneous existence of a gate delay fault and a clock delay fault, some heuristic parameters are introduced in order to compensate the difference between the dictionaries and the responses in a circuit under diagnosis.