DocumentCode
2439494
Title
QoS aware BiNoC architecture
Author
Lo, Shih-Hsin ; Lan, Ying-Cherng ; Yeh, Hsin-Hsien ; Tsai, Wen-Chung ; Hu, Yu-Hen ; Chen, Sao-Jie
Author_Institution
Grad. Inst. of Electron. Eng., Nat. Taiwan Univ., Taipei, Taiwan
fYear
2010
fDate
19-23 April 2010
Firstpage
1
Lastpage
10
Abstract
A quality-of-service (QoS) aware, bi-directional channel NoC (BiNoC) architecture is proposed to support guarantee-service (GS) traffic while reducing packet delivery latency. By incorporating dynamically self-reconfigured bidirectional communication channels between adjacent routers, BiNoC architecture promises more flexibility for various traffic flow patterns. A novel inter-router communication protocol is proposed that prioritizes bandwidth arbitration in favor of high priority GS traffic flows. Multiple virtual channels with prioritized routing policy are also implemented to facilitate data transmission with QoS considerations. Combining these architectural innovations, the QoS aware BiNoC promises reduced latency of packet delivery and more efficient channel resource utilizations. Cycle-accurate simulations demonstrate significant performance advantage over conventional unidirectional NoC architecture equipped with hard-wired unidirectional channels.
Keywords
network-on-chip; quality of service; routing protocols; telecommunication traffic; QoS aware BiNoC architecture; adjacent routers; bandwidth arbitration; bi-directional channel NoC architecture; channel resource utilizations; cycle-accurate simulations; data transmission; dynamically self-reconfigured bidirectional communication channels; guarantee-service traffic; hard-wired unidirectional channels; inter-router communication protocol; multiple virtual channels; network-on-chip; packet delivery latency reduction; quality-of-service; traffic flow patterns; Bandwidth; Bidirectional control; Data communication; Delay; Network-on-a-chip; Protocols; Quality of service; Routing; Technological innovation; Traffic control; Bidirectional Channel; Network-on-Chip; Quality-of-Service; Reconfigurable;
fLanguage
English
Publisher
ieee
Conference_Titel
Parallel & Distributed Processing (IPDPS), 2010 IEEE International Symposium on
Conference_Location
Atlanta, GA
ISSN
1530-2075
Print_ISBN
978-1-4244-6442-5
Type
conf
DOI
10.1109/IPDPS.2010.5470359
Filename
5470359
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