An optimal floating-point pipeline CMOS CORDIC processor

Author

de Lange, A.A.J. ; van der Hoeven, A.J. ; Deprettere, E.F. ; Bu, J.

Author_Institution

Delft Univ. of Technol., Netherlands

fYear

1988

fDate

7-9 June 1988

Firstpage

2043

Abstract

The authors present a VLSI CORDIC processor which is obtained using the hierarchical and interactive design methodology on which the DELFT VLSI synthesis is built. They also present an optimized (floating-point) CORDIC algorithm, the hierarchical mapping of this algorithm on a floating-point architecture, the design method, the layout, the chip, and its performance. Algorithm, architecture, and layout are parameterized with respect to the accuracy of rotation angles and vectors. The CORDIC chip is a pipeline that performs 10/sup 7/ plane rotations/s and is mounted in a 144-pin package. The vector entries are 21 bit floating-point numbers (16-bit mantissa and 5 bit exponent in twos complement).<>

Keywords

CMOS integrated circuits; VLSI; circuit layout CAD; digital arithmetic; microprocessor chips; pipeline processing; 144-pin package; DELFT VLSI synthesis; VLSI CORDIC processor; floating-point architecture; floating-point pipeline CMOS CORDIC processor; hierarchical design; interactive design; layout; rotation angles; Algorithm design and analysis; Analytical models; CMOS process; Circuit simulation; Design methodology; Macrocell networks; Pipelines; Signal processing algorithms; Silicon compiler; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 1988., IEEE International Symposium on

Conference_Location

Espoo, Finland

Type

conf

DOI

10.1109/ISCAS.1988.15343

Filename

15343