High voltage resistant ESD protection circuitry for 0.5 /spl mu/m CMOS OTP/EPROM programming pin

Author

Schröder, H.U. ; van Steenwijk, G. ; Notermans, G.

Author_Institution

Philips Semicond., Zurich, Switzerland

fYear

1998

fDate

6-8 Oct. 1998

Firstpage

96

Lastpage

103

Abstract

This work introduces new high voltage resistant ESD protection circuitry for the programming pin of a nonvolatile one time programmable silicided 0.5 /spl mu/m CMOS device. TLM, HBM, and MM0.75 /spl mu/H ESD stress measurements of this new design resulted in latch-up resistant protection circuitry with an ESD performance of more than 8.0 kV HBM and 950 V MM0.75 /spl mu/H.

Keywords

CMOS memory circuits; EPROM; PLD programming; electrostatic discharge; integrated circuit design; integrated circuit measurement; integrated circuit reliability; microprogramming; protection; standards; 0.5 micron; 8 kV; 950 V; CMOS OTP/EPROM programming pin; ESD performance; HBM ESD stress measurements; HV resistant ESD protection circuitry; MM0.75 microH ESD stress measurements; TLM ESD stress measurements; high voltage resistant ESD protection circuitry; latch-up resistant protection circuitry; nonvolatile one time programmable silicided CMOS device; programming pin; Breakdown voltage; CMOS process; Circuits; Diodes; EPROM; Electrostatic discharge; Nonvolatile memory; Protection; Resistors; Thyristors;

fLanguage

English

Publisher

ieee

Conference_Titel

Electrical Overstress/Electrostatic Discharge Symposium Proceedings, 1998

Conference_Location

Reno, NV, USA

Print_ISBN

1-878303-91-0

Type

conf

DOI

10.1109/EOSESD.1998.737026

Filename

737026