Development of a 64kb MRAM and a study on the magnetization reversal in sub-/spl mu/m sized magnetic tunnel junctions

Author

Lee, Suyoun ; Park, J.H. ; Kim, H.J. ; Koh, K.H. ; Jeong, G.T. ; Jeong, W.C. ; Oh, J.H. ; Hwang, I.J. ; Jeong, H.S. ; Kim, K.N.

fYear

2003

fDate

16-18 Sept. 2003

Firstpage

163

Lastpage

166

Abstract

We have demonstrated a fully integrated 64 kb MRAM using 0.24 /spl mu/m CMOS technology. We found that the etching of magnetic tunnel junctions (MTJ) was likely to bring about an electrical short between the top and bottom of an MTJ, and capping MTJs after etching was very effective in preventing the short. Besides, we performed a lot of magnetic transport measurements of magnetic tunnel junctions during the development and found that the magnetization reversal was affected by some geometrical factors of an MTJ.

Keywords

CMOS memory circuits; magnetic storage; magnetic tunnelling; magnetisation reversal; random-access storage; 0.24 micron; 64 kbit; CMOS technology; MTJ capping; integrated MRAM; magnetic random access memory; magnetic transport measurements; magnetic tunnel junction etching; magnetization reversal; nonvolatile memory; process integration; CMOS process; CMOS technology; Etching; Laboratories; Magnetic materials; Magnetic semiconductors; Magnetic switching; Magnetic tunneling; Magnetization reversal; Semiconductor materials;

fLanguage

English

Publisher

ieee

Conference_Titel

European Solid-State Device Research, 2003. ESSDERC '03. 33rd Conference on

Conference_Location

Estoril, Portugal

Print_ISBN

0-7803-7999-3

Type

conf

DOI

10.1109/ESSDERC.2003.1256836

Filename

1256836