Design of high-voltage devices in a fully implanted twin-well CMOS process

Author

Santos, P.M. ; Quaresma, H. ; Silva, A.P. ; Lanca, M.

Author_Institution

Instituto de Telecomunicacoes, Inst. Superior Tecnico, Lisboa, Portugal

fYear

2003

fDate

16-18 Sept. 2003

Firstpage

343

Lastpage

346

Abstract

Experimental results presented in this paper confirm gate-shifting as an efficient drain engineering technique to increase the breakdown voltage of extended drain high-voltage NMOS transistors to be fabricated in last generation CMOS processes. Breakdown voltages of the order of 30 V can be achieved for gate-shifted LDD NMOS devices fabricated in a fully implanted twin-well 0.5 /spl mu/m CMOS process, aimed for digital applications, without process modification or any additional mask.

Keywords

power MOSFET; semiconductor device breakdown; 0.5 micron; 30 V; LDD NMOS devices; NMOS transistor breakdown voltage; extended drain NMOS transistors; fully implanted CMOS process; gate-shifted NMOS devices; gate-shifting drain engineering technique; high-voltage NMOS transistors; twin-well CMOS process; BiCMOS integrated circuits; CMOS process; CMOS technology; Integrated circuit technology; MOS devices; MOSFETs; Power integrated circuits; Prototypes; Switching circuits; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

European Solid-State Device Research, 2003. ESSDERC '03. 33rd Conference on

Conference_Location

Estoril, Portugal

Print_ISBN

0-7803-7999-3

Type

conf

DOI

10.1109/ESSDERC.2003.1256884

Filename

1256884