The impact of channel engineering on the performance reliability and scaling of CHISEL NOR flash EEPROMs

Author

Mohapatra, Nihar R. ; Nair, Deleep R. ; Mahapatra, S. ; Rao, V. Ramgopal ; Shukuri, S.

Author_Institution

Dept. of Electr. Eng., Indian Inst. of Technol., Bombay, India

fYear

2003

fDate

16-18 Sept. 2003

Firstpage

541

Lastpage

544

Abstract

The programming performance, cycling endurance and scaling of CHISEL NOR flash EEPROMs is studied for two different (halo and no-halo) channel engineering schemes. Programming speed under identical bias, bias requirements under similar programming time, cycling endurance and drain disturb are compared. The scaling properties of programming time (at a fixed bias), bias (at a fixed programming time) and program/disturb margin are studied as cell floating gate length is scaled. The relative merits of these channel engineering schemes are discussed from the viewpoint of futuristic CHISEL cell design.

Keywords

NOR circuits; flash memories; integrated circuit reliability; CHISEL programming mechanism; EEPROM performance reliability; EEPROM scaling; NOR flash EEPROM; cell floating gate length; channel initiated secondary electron injection; cycling endurance; drain disturb; no-halo channel engineering; program/disturb margin; programming speed; Design engineering; Doping; EPROM; Implants; Integrated circuit reliability; Integrated circuit technology; Performance evaluation; Power engineering and energy; Reliability engineering; Semiconductor device reliability;

fLanguage

English

Publisher

ieee

Conference_Titel

European Solid-State Device Research, 2003. ESSDERC '03. 33rd Conference on

Conference_Location

Estoril, Portugal

Print_ISBN

0-7803-7999-3

Type

conf

DOI

10.1109/ESSDERC.2003.1256933

Filename

1256933