Performance Evaluation of an SIMD Architecture with a Multi-bank Vector Memory Unit

The SIMD architecture is very efficient for multimedia data processing since it can handle multiple data with a single instruction. In order to perform an SIMD operation, data must be aligned in the vector register at first, which requires shuffle, pack or unpack instructions and such instructions can be an obstacle to the performance enhancement. The alignment restriction also hinders the efficient automatic vectorization in SIMD compilers. In this paper, an SIMD processor with a multi-bank vector memory unit is designed. The SIMD processor consists of a 2-way VLIW processor, an n-way SIMD co-processor, and an (n+1)-bank vector memory unit. The vector memory unit also includes the address generation logic. An SIMD compiler which exploits the vector memory unit is developed. Since the vector memory permits unaligned and stride accesses without overhead instructions, the developed compiler shows a quite good performance. The performance of an MPEG2 encoder that is optimized by the developed SIMD compiler is analyzed