Memory access characteristics of H.264 video encoder on embedded processor

Several studies have shown memory as performance bottleneck in desktop computers. However, embedded systems differ from workstations and research reports on their memory characteristics are rare. In this paper, we evaluate data and instruction memory in an exemplary handheld device. The simulated system has a CPU core, L1 and L2 cache, interconnect, instruction ROM, and Mobile DDR SDRAM in two clock domains. The memory load is software-based H.264/MPEG-4 AVC video encoder. The results show a non-uniform distribution of the memory accesses and that the length of a DRAM burst is primarily induced by the L2 cache line length. However, further evaluations show that several times longer bursts could be exploited by the application.