Determining the minimum energy operating point for embedded SRAM memory

Reducing power consumption is a major concern in mobile applications, since they are battery operated and require high performance. In this paper, a novel technique to reduce the power consumed by embedded SRAM memory is introduced. The proposed method is an on-chip circuit to measure the optimal data retention voltage (DRV) of the SRAM array. The implemented DRV computing circuit consists of a built-in-self-test (BIST) unit, a DC-DC converter and some control logic. The proposed technique can be used to accurately measure the DRV to ensure the SRAM operates at its minimum energy point. The circuit was developed in 90nm technology and simulated using HSPICE. Monte-Carlo simulation of 100k samples determined the DRV as 150mV whereas the proposed technique showed that the DRV of the SRAM under test could be lowered to 80mV which would result in significant power savings.