Low-power adder design techniques for noise-tolerant applications

In the nanometer era, there is a critical need for low power design. In this paper we employ voltage scaling in a new sophisticated manner to reduce the power consumption of a particular circuit targeted for noise-tolerant applications. We show that we can save up to 40 times in power consumption in the case of applications that can tolerate long delays. On the other hand, we investigate how far we can reduce the power consumption of a circuit without affecting its speed of operation. Our results show 58% and 168% reduction in the power consumption when using multi supply voltages, with the drawback of having some errors in the major reduction technique (168%) which could be suitable for applications that can tolerate some loss of accuracy such as the case in stochastic processing. For such applications, we also show that we can even go further into power savings by eliminating altogether the least significant part of our circuit and hence accepting errors for an additional savings of 41% over the savings in the previous methods.