Integrated energy-aware cyclic and acyclic scheduling for clustered VLIW processors

The technological trend towards smaller feature size and related implications of reduced threshold voltage and increased number of transistors pose a power management challenge. Leakage power dominates total processor power in smaller technologies. In VLIW and clustered VLIW architectures, the large number of functional units with relatively simpler issue logic contribute significantly to the overall power consumption. The underutilization of functional units (because of inherent limitations in ILP among others) causes a significant amount of this power to be consumed in the form of leakage power. Architectural schemes proposed in the past suffer from a limited program view thereby compromising a good amount of energy savings in the form of extra transitions to/from low leakage mode. Energy aware scheduling in the context of VLIW architectures has mostly focused on acyclic scheduling. In this paper, we propose a simple and integrated compiler directed scheme that obtains significant energy savings in functional units for VLIW and clustered VLIW and works equally well for both cyclic as well as acyclic scheduled regions. Our compiler directed scheme increases energy savings in functional units up to 9% and 26% in VLIW architecture and clustered VLIW architecture respectively. We provide a preliminary experimental analysis of our algorithms using the Trimaran 4.0 compiler infrastructure.