Modeling line edge roughness effects in sub 100 nanometer gate length devices

Author

Oldiges, Phil ; Lin, Qinghuang ; Petrillo, Karen ; Sanchez, Martha ; Ieong, Meikei ; Hargrove, Mike

Author_Institution

IBM SRDC, Hopewell Junction, NY, USA

fYear

2000

fDate

2000

Firstpage

131

Lastpage

134

Abstract

A fast method to estimate the effects of line edge roughness is proposed. This method is based upon the use of multiple 2D device “slices” sandwiched together to form a MOS transistor of a given width. This method was verified to yield an accurate representation of rough edge MOS transistors through comparisons to full three dimensional simulations. A subsequent statistical study shows how the variation in line edge roughness affects the values and variances of several key device parameters

Keywords

MOSFET; nanotechnology; rough surfaces; semiconductor device models; statistical analysis; 100 nm; 3D simulations; MOS transistor; device parameters; gate length; line edge roughness; line edge roughness effects modeling; line edge roughness variation; multiple 2D device slices; rough edge MOS transistors; statistical study; Character generation; Extraterrestrial measurements; Length measurement; MOSFETs; Monte Carlo methods; Nanoscale devices; Performance analysis; Performance evaluation; Resists; Space technology;

fLanguage

English

Publisher

ieee

Conference_Titel

Simulation of Semiconductor Processes and Devices, 2000. SISPAD 2000. 2000 International Conference on

Conference_Location

Seattle, WA

Print_ISBN

0-7803-6279-9

Type

conf

DOI

10.1109/SISPAD.2000.871225

Filename

871225