Exact grading of multiple path delay faults

Author

Padmanaban, Saravanan ; Tragoudas, Spyros

Author_Institution

Dept. of Electr. & Comput. Eng., Southern Illinois Univ., Carbondale, IL, USA

fYear

2002

fDate

2002

Firstpage

84

Lastpage

88

Abstract

The problem of fault grading for multiple path delay faults is studied and a method of obtaining the exact coverage is presented. The faults covered are represented and manipulated as sets by zero-suppressed binary decision diagrams (ZBDD), which are shown to be able to store a very large number of path delay faults. For the extreme case of memory problem, a method to estimate the coverage of the test set is also presented. The problem of fault grading is solved with a polynomial number of BDD operations. Experimental results on the ISCAS´85 benchmark include test sets from ATPG tools and specifically designed tests in order to investigate the limitations and properties of the proposed method

Keywords

automatic test pattern generation; binary decision diagrams; combinational circuits; delays; fault diagnosis; logic testing; ATPG tools; BDD operations; ISCAS´85 benchmark; coverage; exact coverage; fault grading; limitations; multiple path delay faults; path delay faults; polynomial number; properties; test sets; zero-suppressed binary decision diagrams; Benchmark testing; Binary decision diagrams; Boolean functions; Circuit faults; Circuit testing; Data structures; Fault diagnosis; Polynomials; Propagation delay; Timing;

fLanguage

English

Publisher

ieee

Conference_Titel

Design, Automation and Test in Europe Conference and Exhibition, 2002. Proceedings

Conference_Location

Paris

ISSN

1530-1591

Print_ISBN

0-7695-1471-5

Type

conf

DOI

10.1109/DATE.2002.998253

Filename

998253