Development of 60V PMOS for power management applications

The paper describes the development of 60V cmos transistor for 0.18-μm Power Management shallow N Buried Layer (NBL) Platform. The device has four terminals, designed to sustain 60V. While the power implants in the platform supports drain-to-source voltage up to 60V, the gate-to-source voltage is limited to 5V by the gate oxide thickness. To extend the attainable gate-to-source voltage, a local oxidation module was used to form the gate oxide. The paper addresses major process and device challenges. Feasibility experiment results are described, and a second experiment aiming to reduce the threshold voltage and increase the breakdown voltage above 80V is discussed.