DocumentCode
2454911
Title
A Radix-10 Combinational Multiplier
Author
Lang, Tomás ; Nannarelli, Alberto
Author_Institution
Dept. of Electr. Eng. & Comput. Sci., Univ. of California, Irvine, CA
fYear
2006
fDate
Oct. 29 2006-Nov. 1 2006
Firstpage
313
Lastpage
317
Abstract
In this work, we present a combinational decimal multiply unit which can be pipelined to reach the desired throughput. With respect to previous implementations of decimal multiplication, the proposed unit is combinational (parallel) and not sequential, has a simpler recoding of the operands which reduces the number of partial product precomputations and uses counters to eliminate the need of the decimal equivalent of a 4:2 adder. The results of the implementation show that the combinational decimal multiplier offers a good compromise between latency and area when compared to other decimal multiply units and to binary double-precision multipliers.
Keywords
combinational circuits; counting circuits; multiplying circuits; pipeline arithmetic; adder; counter; operand recoding; partial product precomputation; pipeline arithmetic; radix-10 combinational decimal multiplier; Arithmetic; Computer science; Counting circuits; Delay; Hardware; Informatics; Throughput;
fLanguage
English
Publisher
ieee
Conference_Titel
Signals, Systems and Computers, 2006. ACSSC '06. Fortieth Asilomar Conference on
Conference_Location
Pacific Grove, CA
ISSN
1058-6393
Print_ISBN
1-4244-0784-2
Electronic_ISBN
1058-6393
Type
conf
DOI
10.1109/ACSSC.2006.354758
Filename
4176568
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