Proposal of the method for high efficiency DC-DC converters and the efficiency limit restricted by silicon properties

In this paper, we analyzed details of power loss in DC-DC converters and proposed the method for improving efficiency. Before the analysis was carried out, we verified the accuracy of SPICE simulation for DC-DC converters by comparing with measured data and a result from 3D electromagnetic simulation which can solve the entire device package and PCB directly. After that, we analyzed the details of the influence of various parasitic inductances on the efficiency by the circuit simulator. The power loss does not decrease monotonically as the parasitic inductance decrease. This is because high side turn-on loss increases as the parasitic inductance decreases. A large voltage drop occurs across the high side MOSFET, because the parasitic inductance is too small to restrict the di/dt. The total parasitic inductance in the main current path for the MCM module is chosen to be equivalent to the optimum value. One of the most important design parameters is the total resistance in the gate driver circuit for power MOSFETs because it is important to reduce the gate resistance in order to reduce high side switching loss and to achieve a short dead time without causing self-turn-on of the low side MOSFET. Finally, we discussed maximum DC-DC converter efficiency restricted by silicon limit. It is predicted that the maximum efficiency for ideal silicon MOSFET is 96% for 1 MHz. The results predict that the switching frequency is limited to as high as 5 MHz, if we assume more than 86% conversion efficiency, as far as the large current, 12 V input voltage VRM are concerned.