An incremental algorithm for test generation in Illinois scan architecture based designs

Author

Pandey, Amit R. ; Patel, Janak H.

Author_Institution

Center for Reliable & High Performance Comput., Illinois Univ., Urbana, IL, USA

fYear

2002

fDate

2002

Firstpage

368

Lastpage

375

Abstract

As the complexity of VLSI circuits is increasing due to the exponential rise in transistor count per chip, testing cost is becoming an important factor in the overall integrated circuit (IC) manufacturing cost. This paper addresses the issue of decreasing test cost by lowering the test data bits and the number of clock cycles required to test a chip. We propose a new incremental algorithm for generating tests for Illinois Scan Architecture (ILS) based designs and provide analysis of test data and test time reduction. This algorithm is very efficient in generating tests for a number of ILS-designs in order to find the most optimal configuration

Keywords

VLSI; automatic test pattern generation; digital integrated circuits; integrated circuit testing; logic testing; production testing; IC manufacturing cost; Illinois scan architecture based designs; VLSI circuits; automatic test pattern generator; clock cycles reduction; incremental algorithm; scan-based ATPG; test cost reduction; test data bits reduction; test set generation; test time reduction; Algorithm design and analysis; Automatic test pattern generation; Built-in self-test; Circuit testing; Computer architecture; Costs; Electronic switching systems; Hip; Integrated circuit testing; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

Design, Automation and Test in Europe Conference and Exhibition, 2002. Proceedings

Conference_Location

Paris

ISSN

1530-1591

Print_ISBN

0-7695-1471-5

Type

conf

DOI

10.1109/DATE.2002.998300

Filename

998300