Optimization of the channel lateral strain profile for improved performance of multi-gate MOSFETs

Author

De Michielis, L. ; Moselund, K.E. ; Bouvet, D. ; Dobrosz, P. ; Olsen, S. ; O´Neill, A. ; Lattanzio, L. ; Najmzadeh, M. ; Selmi, L. ; Ionescu, A.M.

Author_Institution

Nanoelectronic Devices Lab. (Nanolab), Ecole Polytech. Fed. de Lausanne, Lausanne, Switzerland

fYear

2009

fDate

27-29 April 2009

Firstpage

119

Lastpage

120

Abstract

We report for the first time the optimization of the channel lateral strain profile as a new technological booster for improved performance of multi-gate n-channel MOSFET. We find that quasi-uniform or flat-Gaussian-close-to-the-drain profiles are optimum for the I_on boosting of sub-50 nm scaled MOSFETs, while the penalty on I_off and subthreshold slope is minimum. The reported predictions use realistic lateral uniaxial strain profiles, with peaks up to few GPa´s and average values of hundreds of MPa´s.

Keywords

MOSFET; nanoelectronics; optimisation; flat-Gaussian-close-to-the-drain profile; lateral uniaxial strain profile; multigate n-channel MOSFET; optimized channel lateral strain profile technique; Capacitive sensors; Deformable models; Electron mobility; MOSFETs; Nanoscale devices; Semiconductor process modeling; Silicon; Strain measurement; Stress; Tensile strain;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Technology, Systems, and Applications, 2009. VLSI-TSA '09. International Symposium on

Conference_Location

Hsinchu

ISSN

1524-766X

Print_ISBN

978-1-4244-2784-0

Electronic_ISBN

1524-766X

Type

conf

DOI

10.1109/VTSA.2009.5159319

Filename

5159319