FinFET resistance mitigation through design and process optimization

Author

Wang, Cindy ; Chang, Josephine ; Lin, Chung-Hsun ; Kumar, Arvind ; Gehring, Andreas ; Cho, Jin ; Majumdar, Amlan ; Bryant, Andreas ; Ren, Zhibin ; Chan, Kevin ; Kanarsky, Thomas ; Wang, Xinlin ; Dokumaci, Omer ; Guillorn, Michael ; Khater, Marwan ; Yang,

fYear

2009

fDate

27-29 April 2009

Firstpage

127

Lastpage

128

Abstract

The intrinsic FinFET device structure can provide an estimated 10-20% reduction in delay relative to planar FETs at the 22 nm technology node due to superior electrostatics. However, FinFETs are more prone to parasitic resistance and capacitance due to the thin body channel and 3-dimensional device architecture. Here we present strategies for minimizing FinFET parasitic resistance, and discuss overall device design optimization. Using FinFETs built at 45 nm node dimensions, we have demonstrated FinFETs with an NFET/PFET external resistance of 230/350 Omega-um.

Keywords

MOSFET; circuit CAD; FinFET; design optimization; parasitic resistance; process optimization; resistance mitigation; size 22 nm; size 45 nm; Contact resistance; Degradation; Delay estimation; Design optimization; Doping; Electrostatics; FinFETs; Immune system; Parasitic capacitance; Process design; FinFET; parasitic resistance;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Technology, Systems, and Applications, 2009. VLSI-TSA '09. International Symposium on

Conference_Location

Hsinchu

ISSN

1524-766X

Print_ISBN

978-1-4244-2784-0

Electronic_ISBN

1524-766X

Type

conf

DOI

10.1109/VTSA.2009.5159323

Filename

5159323