FPGA implementation of E1 Time Space Time switch

The basic aim of this paper is to see the issue of design entry for implementation and its verification using FPGA Spartan 6. E1 frame format is used for transmission of the data at the rate of the 2.024Mbps. Two stages of the Time switches are used for interchanging the samples and single space switch for interchanging the samples between physical E1 links. Time switch provides the full availability of the channels and same way space switch provides the non-blocking information at the destination. For reference the digital cross-point Time Space switch is used. It has two stages Time space Switch with 8 E1 input Links, all 8 E1 input link is having only one Time switch and one space switch. Each E1 link provides transmission rate of 2.048Mbps. The Time Space Time switch which has been implemented having 2 E1 links. At the end functionality check using truth table and analysis done by using logic analyser to see the change of the data at the rate of 125μsec. At last output Time slot is analysed over the logic analyser to see that 8 bit samples are updated at the rate of 125μsec.