DocumentCode
2456810
Title
A CMOS quaternary latch
Author
Current, K.W.
Author_Institution
Dept. of Electr. Eng. & Comput. Sci., California Univ., Davis, CA, USA
fYear
1989
fDate
29-31 May 1989
Firstpage
54
Lastpage
57
Abstract
A CMOS current-mode quaternary threshold logic latch circuit is proposed. This circuit accepts and requantizes quaternary logical currents during a setup clock mode and latches the input value during the hold clock mode. Using logical current increments of 10 μA, the quaternary latch has been simulated to have a worst-case, three-logical-level transition, total setup and hold time of about 40 ns, and a single-level transition total setup and hold time of about 10 ns
Keywords
CMOS integrated circuits; flip-flops; logic circuits; ternary logic; 10 muA; 10 ns; 40 ns; CMOS quaternary latch; current-mode quaternary threshold logic latch circuit; setup clock mode; three-logical-level transition; CMOS logic circuits; Clocks; Conductors; Fabrication; Integrated circuit interconnections; Integrated circuit technology; Latches; Multivalued logic; Signal processing; Very large scale integration;
fLanguage
English
Publisher
ieee
Conference_Titel
Multiple-Valued Logic, 1989. Proceedings., Nineteenth International Symposium on
Conference_Location
Guangzhou
Print_ISBN
0-8186-1947-3
Type
conf
DOI
10.1109/ISMVL.1989.37759
Filename
37759
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