A Fast-Lock Analog Multiphase Delay-Locked Loop Using a Dual-Slope Technique

In this paper, a fast-lock analog delay-locked loop (DLL) using the dual-slope technique is presented. The architecture of the proposed DLL uses an improved charge pump and two kinds of the phase detector to achieve faster locking time, smaller area cost, and better jitter performance. The DLL was designed using a 0.35 μm standard CMOS process with a 3.3 V supply voltage. The simulation results show that the proposed DLL can be operated correctly when the input clock frequency is changed from 140 MHz to 270 MHz and generate equally spaced eight-phase clocks. When the input clock frequency is 230 MHz, the peak-to-peak jitter is 3.2 ps and the static phase error is 4.1 ps. Moreover, the locking time is 88 clock cycles, the power consumption is 10.8 mW, and core area is 0.069 mm².