A Study on the Cache Miss Rate in a Genetic Algorithm Implementation

As the hardware technology advances, the conventional software development approaches would not effective to conduct an efficient algorithm for run-time environments. The problem comes from the over-simplified hardware abstraction model in software development. The mismatch between the hardware model and the real hardware design should be compensated in designing an efficient algorithm. In this study, we focus on the memory hierarchy and the algorithm design. Both the cache properties and the cache-aware development are investigated. We then propose a few simple guidelines for revising a developed algorithm to increase the utilization of the cache. We also apply the guidelines to a simple genetic algorithm program to verify their effectiveness. The simulation results show that the guidelines are potentially helpful for revising various algorithms.