Quotient Pipelined Very High Radix Scalable Montgomery Multipliers

This paper describes the FPGA implementation of a scalable very high radix Montgomery multiplier using quotient pipelining. It improves upon previous designs by removing critical dependencies between successive processing elements. This design can perform 1024-bit modular exponentiation in 5.1 ms using 3825 4-input lookup tables and 32 18 times 18 multipliers, a 20% speed increase over a comparable design without quotient pipelining.