Delay-Line Sharing Based: A New CMOS Digital PWM Circuit

This paper presents a design of new circuit for digital pulse-width modulators (DPWM). In this paper, we improve the structure of hybrid DPWM to more compact architecture by utilization of the separation of MSB and LSB groups. In addition, a delay-line element is shared by MSB and LSB groups to reduce the power consumption. HSPICE post-layout simulation shows that this new DPWM circuit operates successfully at clock frequency of 200 MHz and has 1.55-mW power consumption. An experimental chip had been fabricated by using a standard 0.18 micron CMOS process. The layout area of the chip including I/O pads is 461 μm × 370 μm. The new DPWM design is with advantages of smaller chip area and low power consumption especially for PWM with high resolution requirement.