Level Compaction in Quantum Circuits

Efficiency of a quantum computation realized in a circuit form depends on many parameters including (but not limited to) the number of gates, the number of auxiliary bits and the number of logic levels. While researchers paid some attention to the minimization of the number of gates and the number of auxiliary bits, the problem of minimizing the number of levels was set aside. However, gates that do not involve the same bits may be applied in parallel. In this paper we present an automated level compactor for quantum circuits. At its core are the templates -a local optimization tool developed for quantum/reversible circuit simplification. We show how the templates can be applied to compact logic levels in quantum circuits, which extends the boundaries of their usefulness. While our method for level compaction is basic, its application to the benchmark circuit specifications shows it has good potential.