Region of nearly constant off current versus gate length characteristics for sub-0.1 μm low power CMOS technology

A minimum in the off current versus gate length characteristics can occur at a threshold voltage maximum for MOS transistors. Sometimes, instead of a minimum, an inflection point can occur at a threshold voltage maximum. We observed that more than one minimum can be experimentally seen. These multiple off current minima can interact with each other and inflection points to create a large range of gate lengths with around the same off current.