• DocumentCode
    2469381
  • Title

    Overview of the MPSoC design challenge

  • Author

    Martin, Grant

  • Author_Institution
    Tensilica, Inc., Santa Clara, CA
  • fYear
    0
  • fDate
    0-0 0
  • Firstpage
    274
  • Lastpage
    279
  • Abstract
    We review the design challenges faced by MPSoC designers at all levels. Starting at the application level, there is a need for programming models and communications APIs that allow applications to be easily re-configured for many different possible architectures without tedious rewriting, while at the same time ensuring efficient production code. Synchronisation and control of task scheduling may be provided by RTOS´s or other scheduling methods, and the choice of programming and threading models, whether symmetric or asymmetric, has a heavy influence on how best to control task or thread execution. Debugging MP systems for the typical application developer becomes a much more complex job, when compared to traditional single-processor debug, or the debug of simple MP systems that are only very loosely coupled. The interaction between the system, applications and software views, and processor configuration and extension, adds a new dimension to the problem space. Zeroing in on the optimal solution for a particular MPSoC design demands a multi-disciplinary approach. After reviewing the design challenges, we end by focusing on the requirements for design tools that may ameliorate many of these issues, and illustrate some of the possible solutions, based on experiments
  • Keywords
    logic design; multiprocessing systems; system-on-chip; MPSoC design; programming models; single-processor debug; system-on-chip; task scheduling methods; thread execution; threading models; Application software; Cellular phones; Embedded system; Energy consumption; Hardware; Permission; Processor scheduling; Software systems; Superluminescent diodes; System-on-a-chip; Design; Experimentation; Languages; MPSoC; Measurement; Multi-Processor System-on-Chip; Performance; System-Level Design; Verification;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Design Automation Conference, 2006 43rd ACM/IEEE
  • Conference_Location
    San Francisco, CA
  • ISSN
    0738-100X
  • Print_ISBN
    1-59593-381-6
  • Type

    conf

  • DOI
    10.1109/DAC.2006.229245
  • Filename
    1688803