DocumentCode
2469857
Title
Random clocking induced DPA attack immunity in FPGAs
Author
Zafar, Yousaf ; Park, Jihan ; Har, Dongsoo
Author_Institution
Dept. of Inf. & Commun., Gwangju Inst. of Sci. & Technol., Gwangju, South Korea
fYear
2010
fDate
14-17 March 2010
Firstpage
1068
Lastpage
1070
Abstract
For FPGA-centric implementations a countermeasure enhancing immunity against differential power analysis (DPA) attacks is proposed, that introduces pseudorandom clocking scheme to Advanced Encryption Standard (AES) cipher based multi-clock system with embedded single inverter ring oscillators (SIROs).
Keywords
clocks; cryptography; field programmable gate arrays; oscillators; AES cipher; FPGA; advanced encryption standard; countermeasure enhancing immunity; differential power analysis attacks; embedded single inverter ring oscillators; multiclock system; pseudorandom clocking scheme; random clocking induced DPA attack immunity; Clocks; Communication standards; Cryptography; Field programmable gate arrays; Frequency; Oscilloscopes; Power supplies; Probes; Reactive power; Resists;
fLanguage
English
Publisher
ieee
Conference_Titel
Industrial Technology (ICIT), 2010 IEEE International Conference on
Conference_Location
Vi a del Mar
Print_ISBN
978-1-4244-5695-6
Electronic_ISBN
978-1-4244-5696-3
Type
conf
DOI
10.1109/ICIT.2010.5472570
Filename
5472570
Link To Document