An Approach to Design a Multiplexer Based Module of a Novel Reversible Gate for FPGA Architecture

The area of reversible logic is attracting much attention of researchers at the present time. Reversible logic concept of digital circuit designing is getting hold of wide scope in the area of nanotechnology, quantum computing, signal processing, optical computing etc due to its capability to design low power loss digital circuits. In this paper a noble reversible gate is proposed. Various classical operations by this proposed gate are shown here. This paper also proposes 2:1 MUX, 4:1 MUX, 8:1 MUX and the design of a reversible multiplexer based module (RMBM) for FPGA architecture using this proposed reversible gate. A comparison between these proposed MUX designs with the existing designs reported in the literature in terms of garbage output, number of gates, constant input and total logical calculation also has been made. Also the proposed gate and a half adder, half subtractor and multiplexer by this proposed gate have been simulated by XILINX and implemented in the SPARTAN -FPGA Kit.