Verification of robustness of digital CMOS circuits

A method to verify that a digital CMOS design is insensitive to variations in process parameters has been developed. During simulation the parts of a design which turn out to be sensitive to variations in detail are pointed out to the designer. This also gives an indication of what parts can be redesigned more aggressively to achieve better performance. Intrachip deviation and interchip deviation are treated separately to avoid inadequate uncertainty