Improving self-timed pipeline ring performance through the addition of buffer loops

While self-timed pipelines have overcome the problem of clock skew which degrades the performance of synchronous pipelines, the improvement is not without its cost; self-timed pipelines are forced to spend a larger amount of time on communication than their synchronous counterparts. This has led researchers to search for ways to improve the performance of self-timed pipelines by changing the communication scheme in an effort to reduce the communication delay. Our approach divides the total communication time into two parts: data communication delay and pace handshaking overhead. By adding buffer loops to each stage of a self-timed pipeline, we can reduce the pace handshaking overhead; thus decreasing the total time spent on communication. One important result of this design innovation has been the simplification of analysis needed to find the best initial system configuration. With our design, the same initial system configuration may be chosen regardless of computation time and variations in computation time. In addition, our design has a lower average cycle time than the traditional self-timed pipeline, which leads to an increase in performance