Prediction of gate delay variation for CNFET under CNT density variation

Author

Shahi, A.A.M. ; Zarkesh-Ha, Payman

Author_Institution

Dept. of Electr. & Comput. Eng., Univ. of New Mexico Albuquerque, Albuquerque, NM, USA

fYear

2012

fDate

3-5 Oct. 2012

Firstpage

140

Lastpage

145

Abstract

This paper presents an analytical model for prediction of gate-delay variation in CNFETs that is caused by CNT density variation. The analytical gate-delay variation model is derived from our previously developed model for CNT density variation using binomial distribution. Our analytical model shows that the percentage of delay variation (σ/μ) due to CNT density variation in a CNFET logic gate is a function of the average number of CNTs. For example, the delay variation of a 1x CNFET inverter with 50 CNTs driving a 200fF load capacitor is expected to be about 10%. However, the delay variation reduces to about 5% in a 4X inverter with 200 CNTs, on average.

Keywords

binomial distribution; carbon nanotube field effect transistors; logic gates; CNFET inverter; CNFET logic gate; CNT density variation; analytical gate-delay variation model; binomial distribution; gate delay variation prediction; load capacitor; Decision support systems; Discrete Fourier transforms; Fault tolerance; Fault tolerant systems; Nanotechnology; Very large scale integration; CNT density variation; Carbon nanotube filed-effect transistor; Carbon nanotubes; Gate dehy;

fLanguage

English

Publisher

ieee

Conference_Titel

Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT), 2012 IEEE International Symposium on

Conference_Location

Austin, TX

Print_ISBN

978-1-4673-3043-5

Type

conf

DOI

10.1109/DFT.2012.6378214

Filename

6378214