Simulation-based hierarchical sizing and biasing of analog firm IPs

This paper presents a simulation-based hierarchical sizing and biasing tool for analog integrated circuits design. The tool allows the designer to express the sizing procedure in terms of sizing and biasing operators. These operators are technology independent, hence the documented procedure can be easily ran over different technologies. A procedure has been proposed for a single-ended two-stage operational amplifier and evaluated over 130 nm, 65 nm and 45 nm technologies. The results prove the efficiency of the proposed tool.