A novel logic level calculation model for leakage currents in digital nano-CMOS circuits

Accurate leakage current estimation in the early phase of digital IC synthesis is an increasingly critical step in the design flow. We present a logic-level estimation approach, suitable for implementation in HDL models or as an off-line tool, supporting separate estimation of the leakage components (sub-threshold, gate tunneling, reverse junction BTBT) including pattern dependency, stacking effects and loading effects. Results on single standard cells and multi-cell circuits exhibit a very good accuracy i.e. below 1% error with respect to Spice BSIM4.