Parameterized free space redistribution for engineering change in placement of integrated circuits

In this paper we present a method for parameterized free space redistribution of a fragmented placement. The fragmentation problem arises in different contexts within the physical design automation, including post physical synthesis for filler cell insertion, incremental placement, timing optimization, and late mode ECO fix-ups. To address this problem, we apply a post-placement parameterized method of defragmentation. This method involves capturing a view of a given placement and modeling a dynamic programming problem to optimally maximize the amount of so-called useful free space as defined by a given set of parameters. The parameters act as constraints to preserve the row placement and order of the cells while minimizing the perturbation of the whole design for a successful timing and design closure. Experimental results demonstrate that by applying the proposed technique, on average, 9.7% increase in the number of inserted filler cells and 5.7% improvement in the success rate of incremental placement requests can be achieved with minimal or no impact on timing and wirelength. Moreover, when deployed in early mode buffering for timing optimization, this technique can result in 3% reduction in the number of paths with negative slacks.