DocumentCode
2482241
Title
Implementation of Modular Multiplication for RSA Algorithm
Author
Sahu, Sushanta Kumar ; Pradhan, Manoranjan
Author_Institution
Dept. of Electron. & Tele-Commun. Eng., Veer Surendra Sai Univ. of Technol., Burla, India
fYear
2011
fDate
3-5 June 2011
Firstpage
112
Lastpage
114
Abstract
This paper presents the architecture and modeling of modular multiplication for RSA public key algorithm. It supports multiple lengths like 128 bits, 256 bits, 512 bits of data. In this paper simple shift and add algorithm is used to implement the modular multiplication. It makes the processing time faster and used comparatively smaller amount of space in the FPGA due to its reusability. Each block is coded with Very High Speed Integrated Circuit Hardware Description Language. The VHDL code is synthesized and simulated using Xilinx-ISE 10.1.
Keywords
field programmable gate arrays; hardware description languages; public key cryptography; FPGA; RSA public key algorithm; VHDL code; Xilinx-ISE 10.1; modular multiplication; very high speed integrated circuit hardware description language; Adders; Classification algorithms; Encryption; Hardware; Public key; Registers; FPGA; RSA; VHDL; modular multiplication;
fLanguage
English
Publisher
ieee
Conference_Titel
Communication Systems and Network Technologies (CSNT), 2011 International Conference on
Conference_Location
Katra, Jammu
Print_ISBN
978-1-4577-0543-4
Electronic_ISBN
978-0-7695-4437-3
Type
conf
DOI
10.1109/CSNT.2011.30
Filename
5966416
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