Audio application implementations on a block-floating-point DSP

Author

Kobayashi, S. ; Lee, S.Z. ; Kino, T. ; Kozuka, I. ; Tokui, T.

fYear

2002

fDate

16-18 Oct. 2002

Firstpage

51

Lastpage

56

Abstract

Hierarchical block-floating-point arithmetic (H-BFP) is applied to a configurable DSP architecture. This new arithmetic has been proposed in order to solve a trade-off problem between complexity and accuracy in implementing conventional block-floating-point arithmetics. This paper describes an actual implementation of the DSP architecture on a field programmable gate array (FPGA) platform. Some signal processing quality evaluation results are also presented for two audio applications that are realized on the DSP architecture.

Keywords

audio signal processing; digital signal processing chips; field programmable gate arrays; floating point arithmetic; FPGA platform; audio applications; configurable DSP architecture; field programmable gate array; hierarchical block-floating-point arithmetic; signal processing quality evaluation; Array signal processing; Costs; Digital signal processing; Field programmable gate arrays; Fixed-point arithmetic; Floating-point arithmetic; Hardware; Laboratories; Mobile communication; Signal processing;

fLanguage

English

Publisher

ieee

Conference_Titel

Signal Processing Systems, 2002. (SIPS '02). IEEE Workshop on

ISSN

1520-6130

Print_ISBN

0-7803-7587-4

Type

conf

DOI

10.1109/SIPS.2002.1049684

Filename

1049684