DocumentCode
2487018
Title
Notice of Violation of IEEE Publication Principles
Efficient implementation of QRD-RLS algorithm using hardware-software co-design
Author
Lodha, N. ; Rai, N. ; Krishnamurthy, A. ; Venkataraman, H.
Author_Institution
Dhirubhai Ambani Inst. of Inf. & Commun. Technol., Gandhinagar, India
fYear
2009
fDate
23-29 May 2009
Firstpage
1
Lastpage
4
Abstract
Notice of Violation of IEEE Publication Principles
"Efficient Implementation of QRD-RLS Algorithm using Hardware-Software Co-design"
by Napur Lodha, Nivesh Rai, Aarthy Krishnamurthy, Hrishikesh Venkataraman
in the 2009 IEEE International Symposium on Parallel & Distributed Processing (IPDPS 2009), 2009, pp. 1 - 4.
After careful and considered review of the content and authorship of this paper by a duly constituted expert committee, this paper has been found to be in violation of IEEE\´s Publication Principles.
This paper contains significant portions of original text from the paper cited below. The original text was reused with insufficient attribution (including appropriate references to the original author(s) and/or paper title) and without permission from all coauthors.
Due to the nature of this violation, reasonable effort should be made to remove all past references to this paper, and future references should be made to the following article:
"Hardware-Software Co-design of QRD-RLS Algorithm with Microblaze Soft Core Processor"
by Napur Lodha, Nivesh Rai, Rahul Dubey, Hrishikesh Venkataraman
in the Third International Conference on Information Systems, Technology and Management (ICISTM-09), 2009, pp. 197 - 207.
This paper presents the implementation of QR Decomposition based Recursive Least Square (QRD-RLS) algorithm on Field Programmable Gate Arrays (FPGA) using hardware-software co-design. The system has been implemented on Xilinx Spartan 3E FPGA with Microblaze soft core processor. The hardware part consists of a custom peripheral that solves the part of the algorithm with higher computational costs and the software part consists of an embedded soft core processor that manages the control functions and rest of the algorithm. The speed and flexibility of FPGAs render them viable for such computationally intensive application. This paper also presents the implementation results and their analysi- .
"Efficient Implementation of QRD-RLS Algorithm using Hardware-Software Co-design"
by Napur Lodha, Nivesh Rai, Aarthy Krishnamurthy, Hrishikesh Venkataraman
in the 2009 IEEE International Symposium on Parallel & Distributed Processing (IPDPS 2009), 2009, pp. 1 - 4.
After careful and considered review of the content and authorship of this paper by a duly constituted expert committee, this paper has been found to be in violation of IEEE\´s Publication Principles.
This paper contains significant portions of original text from the paper cited below. The original text was reused with insufficient attribution (including appropriate references to the original author(s) and/or paper title) and without permission from all coauthors.
Due to the nature of this violation, reasonable effort should be made to remove all past references to this paper, and future references should be made to the following article:
"Hardware-Software Co-design of QRD-RLS Algorithm with Microblaze Soft Core Processor"
by Napur Lodha, Nivesh Rai, Rahul Dubey, Hrishikesh Venkataraman
in the Third International Conference on Information Systems, Technology and Management (ICISTM-09), 2009, pp. 197 - 207.
This paper presents the implementation of QR Decomposition based Recursive Least Square (QRD-RLS) algorithm on Field Programmable Gate Arrays (FPGA) using hardware-software co-design. The system has been implemented on Xilinx Spartan 3E FPGA with Microblaze soft core processor. The hardware part consists of a custom peripheral that solves the part of the algorithm with higher computational costs and the software part consists of an embedded soft core processor that manages the control functions and rest of the algorithm. The speed and flexibility of FPGAs render them viable for such computationally intensive application. This paper also presents the implementation results and their analysi- .
Keywords
field programmable gate arrays; hardware-software codesign; least squares approximations; Microblaze soft core processor; QR decomposition; QRD-RLS Algorithm; Xilinx Spartan 3E FPGA; custom peripheral; field programmable gate arrays; hardware-software co-design; recursive least square algorithm; Application software; Computer architecture; Field programmable gate arrays; Hardware; Least squares approximation; Least squares methods; Matrices; Reconfigurable logic; Resonance light scattering; Software algorithms; Co-design; Microblaze; Xilinx; recursive least square (RLS);
fLanguage
English
Publisher
ieee
Conference_Titel
Parallel & Distributed Processing, 2009. IPDPS 2009. IEEE International Symposium on
Conference_Location
Rome
ISSN
1530-2075
Print_ISBN
978-1-4244-3751-1
Type
conf
DOI
10.1109/IPDPS.2009.5161200
Filename
5161200
Link To Document