The partition algorithm for interconnect analysis in carbon nanotube based ASICs

Bundles of carbon nanotubes (CNTs) have been proposed as a promising replacement for copper interconnect due to their large conductivity and current-carrying capabilities. However, large resistance caused by imperfect metal contacts appears to be a significant problem in short CNT interconnects. Taking advantages of both CNT and copper becomes a good choice in ASIC. In this paper, an effective partition algorithm is proposed, which determines the partition length and makes reasonable allocation for CNT bundles and copper interconnect, thereby optimizing the performance of ASIC. Compared to copper based interconnect, the experiments report the critical delay is reduced to about 29%.