DocumentCode
2488497
Title
GaAs HBT gate array for high performance ASICs
Author
Yinger, Steve ; Lee, Frank ; Huang, R.T. ; Schneider, Karen ; Wang, Ed ; Smith, Kent ; Penugonda, Madhu ; Jacobs, Steve ; Carter, Tony
Author_Institution
Microelectron. Technol. Center, Rockwell Int. Corp., Newbury Park, CA, USA
fYear
1994
fDate
1-4 May 1994
Firstpage
611
Lastpage
614
Abstract
A high speed HBT gate array has been developed for applications requiring data rates up to 5 Gbps. Die size is 2.2 mm×2.2 mm and is packaged in a 68 pin leaded chip carrier with 20 pair of differential I/O signals. Typical power dissipation is 1 to 3 Watts. The array uses three levels of series gating enabling complex logic functions to be implemented efficiently. The top level gate delay is 40 ps for a fanout of one and 60 fF load
Keywords
III-V semiconductors; application specific integrated circuits; bipolar logic circuits; gallium arsenide; heterojunction bipolar transistors; logic arrays; 1 to 3 W; 40 ps; 5 Gbit/s; GaAs; HBT gate array; complex logic functions; high performance ASICs; high speed gate array; leaded chip carrier; Application specific integrated circuits; Delay; Gallium arsenide; Heterojunction bipolar transistors; Logic arrays; Logic design; Logic functions; Logic gates; Power dissipation; Resistors;
fLanguage
English
Publisher
ieee
Conference_Titel
Custom Integrated Circuits Conference, 1994., Proceedings of the IEEE 1994
Conference_Location
San Diego, CA
Print_ISBN
0-7803-1886-2
Type
conf
DOI
10.1109/CICC.1994.379648
Filename
379648
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