A 400 MHz, 300 mW, 8 kb, CMOS SRAM macro with a current sensing scheme

Author

Izumikawa, Hlasaiiori ; Suzuki, Iiazumasa ; Nomura, Masahiro ; Igura, Hiroyuki ; Abiko, Hitoshi ; Okabe, Iiazuhiro ; Ono, Atsuki ; Nakayama, Takashi ; Yamashina, Masakazu ; Yamada, Hachiro

Author_Institution

NEC Corp., Kanagawa, Japan

fYear

1994

fDate

1-4 May 1994

Firstpage

595

Lastpage

598

Abstract

This paper describes the development of a 400 MHz, 8 kb, 0.4 μm CMOS SRAM macro targeted for use in on-chip cache memories. A newly developed pipeline scheme uses a dynamic decoder and half-latches to increase speed by 10% over that of conventional synchronous pipeline SRAMs. Further, a newly developed current sensing scheme, resistant both to noise and to process deviations, contributes to a job reduction in power dissipation

Keywords

CMOS memory circuits; SRAM chips; cache storage; cellular arrays; pipeline processing; 0.4 micron; 300 mW; 400 MHz; 8 kbit; CMOS SRAM macro; current sensing scheme; dynamic decoder; half-latches; job reduction; on-chip cache memories; pipeline scheme; power dissipation; process deviations; Circuits; Decoding; Delay effects; Hip; Latches; National electric code; Pipeline processing; Power dissipation; Random access memory; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Custom Integrated Circuits Conference, 1994., Proceedings of the IEEE 1994

Conference_Location

San Diego, CA

Print_ISBN

0-7803-1886-2

Type

conf

DOI

10.1109/CICC.1994.379652

Filename

379652

Link To Document

https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=2488610